MA300013【PDF 43/92 页】MODULE DSPIC30F SAMPLE 80QFP

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dsPIC30F

TABLE 10-9:

PROGRAM FLOW INSTRUCTIONS

Assembly

BRA

BRA

BRA

BRA

BRA

BRA

BRA

BRA

BRA

BRA

BRA

BRA

BRA

BRA

BRA

BRA

BRA

BRA

BRA

BRA

BRA

BRA

CALL

CALL

DO

DO

GOTO

GOTO

RCALL

RCALL

REPEAT

REPEAT

RETFIE

RETLW

RETURN

Syntax

Expr

Wn

C,Expr

GE,Expr

GEU,Expr

GT,Expr

GTU,Expr

LE,Expr

LEU,Expr

LT,Expr

LTU,Expr

N,Expr

NC,Expr

NN,Expr

NOV,Expr

NZ,Expr

OA,Expr

OB,Expr

OV,Expr

SA,Expr

SB,Expr

Z,Expr

Expr

Wn

#lit14,Expr

Wn,Expr

Expr

Wn

Expr

Wn

#lit14

Wn

#lit10,Wn

Description

Branch unconditionally

Computed branch

Branch if Carry (no Borrow)

Branch if greater than or equal

Branch if unsigned greater than or equal

Branch if greater than

Branch if unsigned greater than

Branch if less than or equal

Branch if unsigned less than or equal

Branch if less than

Branch if unsigned less than

Branch if Negative

Branch if not Carry (Borrow)

Branch if not Negative

Branch if not Overflow

Branch if not Zero

Branch if Accumulator A Overflow

Branch if Accumulator B Overflow

Branch if Overflow

Branch if Accumulator A Saturate

Branch if Accumulator B Saturate

Branch if Zero

Call subroutine

Call indirect subroutine

Do code through PC + Expr, (lit14 + 1) times

Do code through PC + Expr, (Wn + 1) times

Go to address

Go to address indirectly

Relative call

Computed call

Repeat next instruction (lit14 + 1) times

Repeat next instruction (Wn + 1) times

Return from interrupt enable

Return with lit10 in Wn

Return from subroutine

Words

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

1

2

2

2

1

1

1

1

1

1

1

1

Cycles

2

2

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

2

2

2

2

2

2

2

2

1

1

3 (2)

3 (2)

3 (2)

Note 1:

2:

Conditional branch instructions execute in 1 cycle if the branch is not taken, or 2 cycles if the branch is

taken.

RETURN normally executes in 3 cycles. However, it executes in 2 cycles if an interrupt is pending.

? 2005 Microchip Technology Inc.

DS70043F-page 41

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